A FinFET transistor utilizes a channel region which is oriented to conduct an electrical current parallel to the surface of the substrate. The channel region is provided in an elongated section of semiconductor material referred to in the art as a “fin.” The source and drain regions of the transistor are typically also formed in the elongated section on either side of the channel region. A gate is placed over and on both opposed sides of the elongated section at the location of the channel region to provide control over the conductive state of the transistor. This FinFET design is well suited for manufacturing a multi-channel transistor in which multiple elongated sections are formed in parallel to define neighboring channel regions separated from each other by an intermediate gate portion, where the transistor gate spans with a perpendicular orientation over the multiple elongated sections.
It is well known in the art to form the source and drain regions of the transistor using epitaxial growth starting from a top surface of the fin on either side of the gate and channel region. There are number of benefits which accrue from the use of a tall epitaxial growth. First, because of the generally tapered shape of the sidewall spacers for the gate structure, the width between adjacent gate structures increases with height, and thus a taller epitaxial growth will result in a larger surface area at the top of the epitaxial growth for use in siliciding the source or drain contact. Second, increased epitaxial growth height makes the circuit more robust to issues with contact gouging. Third, the profile of the contact etch bottom profile into the epitaxial growth can be tuned to increase contact area if a greater epitaxial growth height is available. Fourth, increased epitaxial growth provides more material for consumption during a salicidation process associated with forming the source/drain contacts. Fifth, there is a lessened risk of shorting. Sixth, the top surface of the epitaxial growth could be patterned with channels or other depth structures to increase the contact area and area available for salicidation.
However, the growth of taller epitaxial regions for the source and drain on the top surface of the fin can violate design spacing rules. There is accordingly a need in the art for a method to better confine epitaxial growth for source and drain regions of FinFET transistor in a manner which permits a taller epitaxial growth with reduced risk of violating design spacing rules.